A charge pump voltage generator is an important circuit for numerous systems and applications for its ability to increase voltage beyond the voltage received from an external power supply. One of the important application is to boost the performance and/or reduce the power of circuits using back-gate bias. However, to generate back-gate bias beyond the supply and ground voltages, a highly efficient charge pump is required so that its power and area overhead does not offset the advantage of the performance boost and power savings.
A conventional charge pump voltage generator circuit design implemented in a bulk complementary metal oxide semiconductor (CMOS) process, wherein the bulk (or back-gate) of a transistor switch is grounded is shown in FIG. 1A. Adverting to FIG. 1A, a switch capacitor charge pump 100 includes a plurality of stages, e.g., four stages 101, 103, 105 and 107. Each of these four stages includes a top half and a bottom half. The top half and the bottom half of each stage includes an n-type field-effect transistor (NFET), a p-type field-effect transistor (PFET) and a capacitor. The back-gate of each NFET (e.g., 109, 113, 117, 121, 125, 129, 133 and 137) is grounded as depicted by the arrow symbol, and the back-gate of each PFET (e.g., 111, 115, 119, 123, 127, 131, 135 and 139) is connected to the drain of each PFET as depicted by the right angle connection. Therefore, the threshold voltage and the “on” state resistance of the transistor switch is higher due to the back-gate effect, especially for switches in the stages that operate at higher generated voltages. This results in higher equivalent resistance, lower output voltage, and lower efficiency when sourcing current. Moreover, the threshold voltage of each transistor switch increases as the source to bulk voltage of each transistor switch increases from one stage to the next stage in a multi-stage charge pump.
A conventional charge pump voltage generator circuit design implemented in isolated well process technology, wherein the isolated well (or back-gate) of transistor switch can be connected to the source is shown in FIG. 1B. Referring to FIG. 1B, the switch capacitor charge pump 140 like the switch capacitor charge pump 100 of FIG. 1A also includes a plurality of stages, e.g., four stages 141, 143, 145 and 147. Each of these four stages includes a top half and a bottom half. The top half and the bottom half of each stage includes an NFET, a PFET and a capacitor. The back-gate of each NFET and PFET (e.g., 149 through 179) is connected to the source of each NFET and PFET, respectively, as depicted by the right angle connection. While the source voltage provides the back-gate bias to reduce the threshold voltage during the “on” state, it is not dynamically switched to a lower voltage during “off” state, hence, the design of FIG. 1B does not provide the other benefit of having higher “off” state resistance and lower leakage. Moreover, the isolated well (or back-gate) can only be connected to the source terminal to avoid the unintended forward biased of the well-diffusion junction diode.
A need therefore exists for methodology enabling the back-gates of a transistor switch of a charge pump voltage generator implemented in an isolated well process technology to be biased with the same voltage generated for the front-gate of each switch.